Knowledge Base

PHY Chip

A PHY Chip is a physical layer in computer networking. PHY is an abbreviation for the physical layer of the OSI model.

An instantiation of PHY connects a link layer device (often called a MAC) to a physical medium such as an optical fiber or copper cable. A PHY device typically includes a Physical Coding Sublayer (PCS) and a Physical Medium Dependent (PMD) layer. The PCS encodes and decodes the data that is transmitted and received. The purpose of the encoding is to make it easier for the receiver to recover the signal.

Example Uses of PHY Chips

  • Wi-Fi: The PHY portion consists of the RF, mixed-signal and analog portions, which are often called transceivers, and the digital baseband portion that place high demand on the digital signal processing (DSP) and communication algorithm processing, including channel codes. It is common that these PHY portions are integrated with the media access control (MAC) layer in System-on-a-chip (SOC) implementations. Other similar wireless applications are 3G/4G/LTE, WiMAX, UWB, etc.
  • Ethernet: A PHY chip (PHYceiver) is commonly found on Ethernet devices. Its purpose is physical, analog signal access to the link. It is usually used in conjunction with an Media Independent Interface (MII) chip or interfaced to a microcontroller that takes care of the higher layer functions.
  • Universal Serial Bus (USB): A PHY chip is integrated into most USB controllers in hosts or embedded systems and provides the bridge between the digital and modulated parts of the interface.
  • IrDA: The Infrared Data Associations (IrDA) specification includes an IrPHY specification for the physical layer of the data transport.
  • Serial ATA (SATA): Serial ATA controllers like the VIA Technologies VT6421 use a PHY.
  • SDRAM chip interfaces
  • Flash memory chip interfaces


Ethernet Physical Transceiver

An Ethernet physical transceiver is often called a PHYceiver. It is a device that operates at the physical layer of OSI network model.

An Ethernet PHYceiver is a chip that implements the hardware send and receive function of Ethernet frames; it interfaces to the line modulation at one end and binary packet signaling at the other. Functions like MAC addressing are implemented by the Media Access Control function. Wake-on-LAN and Boot ROM functionality is implemented in the network interface card (NIC), which may have PHY, MAC and other functionality integrated into one chip or as separate chips.

100 Mbit/s and faster line speeds is implemented with a digital signal processor (DSP) inside the Ethernet PHY.

Some examples of Ethernet PHYceiver chips are Integrated Circuit Systems ICS1893, Realtek RTL8201 and VIA Technologies VIA6103.

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